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  Interrupt Enable Register

The Interrupt Enable Register is probably one of the simplest for understanding in UART. Setting Bit 0 high enables the Received Data Available Interrupt which generates an interrupt when the receiving register/FIFO contains data to be read by the CPU.

Bit 1 enables Transmit Holding Register Empty Interrupt. This interrupts the CPU when the transmitter buffer is empty. Bit 2 enables the receiver line status interrupt. The UART will interrupt when the receiver line status is changed. The same is for bit 3 which enables the modem status interrupt. Bits 4 to 7 are the easy ones. They are simply reserved. (If only everything was that easy!)

Bit 7Reserved
Bit 6Reserved
Bit 5Enables Low Power Mode (16750)
Bit 4Enables Sleep Mode (16750)
Bit 3Enable Modem Status Interrupt
Bit 2Enable Receiver Line Status Interrupt
Bit 1Enable Transmitter Holding Register Empty Interrupt
Bit 0Enable Received Data Available Interrupt
Interrupt Enable Register
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