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  Interrupt Identification Register (IIR)

The interrupt identification register is read-only.

Bit 0 shows if there's been an interrupt, if the interrupt has ocurred the interrupt state is described by bits 1 and 2. The Line Status Interrupt has the highest priority, then goes the Data Available Interrupt, then the Transmit Register Empty Interrupt and then the Modem Status Interrupt which has the lowest priority.

Bit 3 shows the status of the time-out interrupt on a 16550 or higher.

Bits 5 and 4 are reserved.

Bits 6 and 7 contain information about the FIFO buffer state. When both bits = '0', FIFO buffers are inactive. There must be such a result when you use 8250 or 16450.

If bit 7is active while bit 6 is inactive UART reports that the buffers are on but unusable. If both bits are active, FIFO buffers are on and active.

Bit Notes
Bits 6 and 7 Bit 6 Bit 7
0 0 No FIFO
0 1 FIFO Enabled but Unusable
1 1 FIFO Enabled
Bit 5 64 Byte Fifo Enabled (16750 only)
Bit 4 Reserved
Bit 3 0 Reserved on 8250, 16450
1 16550 Time-out Interrupt Pending
Bits 1 and 2 Bit 2 Bit 1
0 0 Modem Status Interrupt
0 1 Transmitter Holding Register Empty Interrupt
1 0 Received Data Available Interrupt
1 1 Receiver Line Status Interrupt
Bit 0 0 Interrupt Pending
1 No Interrupt Pending
Interrupt Identification Register
 
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