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RS232 Hardware
  Line Status Register (LSR)

LSR is a read-only register.

Bit 0 shows that the data is ready, that means that a byte was received in UART and the receiver buffer is ready for reading.

Bit 1 is responsible for overrun error existance. This error usually occurs when the data are read from the port slower than they are received. If you don't read the incoming bytes fast enough the last byte can be overwritten with the byte which was received last, in this case the last byte may be lost which will cause overrun error.

Bit 2 is responsible for parity error existance. This error occurs if the parity doesn' coincide with the parameters set when the byte is received.

Bit 3 is responsible for framing error existance. This error occurs if the last bit is not a stop bit. This generally happens because of synchronization error. You may face this error when connecting two computers with the help of null modem, if the baud rates of the transmitting computer differs from the baud rates of the receiving computer.

Bit 4 is responsible for break interrupt settings. It happens when the received data line is held in a logic state '0' (Space) for more than it takes to send a full word. That includes the time for the start bit, data bits, parity bits and stop bits.

Bit 5 (when set) only shows that transmitter holding register is empty.

Bit 6 (when set) signals that transmitter holding register and the shift register are empty. The UART's holding register contains the next data byte, presented as parallel and ready for transmission. The shift register is used to transform the byte into a serial one, so that the data could be sent with the help of one line.

The difference between bits 5 and 6 is as follows: when bit 6 is set, holding and shift registers are empty and the operations of serial transformation are not carried out as there are no data for transmission. When bit 5 is set, the transmitter holding register is empty, which allows data transmission into the port and transformation into the serial code can be carried out.

Bit 7 signals that an error occurred in Received FIFO when receiving data. This bit has high level if one of the following errors occurred when receiving the bytes contained in the FIFO buffers: break, parity or framing error has occurred.

Bit Notes
Bit 7 Error in Received FIFO
Bit 6 Empty Data Holding Registers
Bit 5 Empty Transmitter Holding Register
Bit 4 Break Interrupt
Bit 3 Framing Error
Bit 2 Parity Error
Bit 1 Overrun Error
Bit 0 Data Ready
Line Status Register
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